Referenced Items are not available for this document.
GENESYS, a hierarchical tool for exploring future ASIC technology and architecture, is described and employed to project high-performance ASIC power drain and clock frequency, a roadmap for interconnect design, and performance, energy, and area limits
Published in:
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Date of Conference: 23-27 Sep 1996
- Page(s):
- 193 - 196
- Meeting Date :
- 23 Sep 1996-27 Sep 1996
- ISSN :
- 1063-0988
- Print ISBN:
- 0-7803-3302-0
- INSPEC Accession Number:
- 5472741
- Conference Location :
- Rochester, NY
- Digital Object Identifier :
- 10.1109/ASIC.1996.551992
- Product Type:
- Conference Publications
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