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In this paper, we present a 4T low-power linear output current-mediated CMOS APS imager, in which reset and read-out operations are carried-out simultaneously on two pixels of the same row. The proposed operating technique greatly simplifies the pixel architecture with only four transistors and two control signals required, while six transistors and four control lines are required by its current-mediated counterpart. The imager achieves fixed pattern noise (FPN) correction during pixel-readout and exhibits a power consumption which is independent of the imager array size, since only a single current source is solicited at any given time due to the array-level operating technique. A linearization circuit technique using the transistor's channel length modulation effect is employed enabling to double the linear range of the pixel's photon-to-output signal transfer function. Performance analysis and experimental results are presented for a 32 × 32 image sensor array prototype, fabricated using AMS 0.35-μm process. The pixel size is 6.5 × 6.5 μm2 with 22% fill-factor. The chip total power consumption is less than 1 mW, at 50 frames/s with a 3.3 V power supply.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:19 , Issue: 9 )
Date of Publication: Sept. 2011