Referenced Items are not available for this document.
A one-transistor tunnel static random access memory (SRAM) cell is proposed and analyzed. The new cell uses the bistability of a tunnel diode pair to latch the body voltage of a MOSFET that then shifts the threshold voltage and enables sensing of the state by the measurement of the MOSFET transistor current. Band-to-band tunneling is used to write the cell. This cell offers more than 10 000× reduction in static power compared to the 6-transistor (T) SRAM at the 32-nm technology node. A cell size of 48F2 is shown, which is comparable to a 6-T SRAM. Access times should be similar to high performance a 6-T SRAM given the same transistor technology.
Published in:
Nanotechnology, IEEE Transactions on
(Volume:11
,
Issue:
6
)
Date of Publication: Nov. 2012
- Page(s):
- 1067 - 1072
- ISSN :
- 1536-125X
- INSPEC Accession Number:
- 13146617
- Digital Object Identifier :
- 10.1109/TNANO.2010.2053555
- Product Type:
- Journals & Magazines
- Date of Publication :
- 21 June 2010
- Date of Current Version :
- 16 November 2012
- Issue Date :
- Nov. 2012
- Sponsored by :
- IEEE Nanotechnology Council
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