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Design and fabrication of a reliability test chip for 3D-TSV

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7 Author(s)
A D Trigg ; Institute of Microelectronics, A¿STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore Science Park II, Singapore 117685 ; Li Hong Yu ; Xiaowu Zhang ; Chai Tai Chong
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A test chip has been designed and fabricated to validate the performance, yield and reliability of 3D chip stacks using Through Silicon Vias (TSVs). The test chip contains test structures designed to measure the electromigration performance of TSVs and microbump, thermal performance, stress in the chip as a result of thinning and die stacking, and corrosion related to moisture ingress. The structures are designed to facilitate failure analysis, allowing fault isolation to be done by electrical characterization as far as possible.

Published in:

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

Date of Conference:

1-4 June 2010