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Synthesis of Reversible Circuits with No Ancilla Bits for Large Reversible Functions Specified with Bit Equations

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3 Author(s)
Alhagi, N. ; Dept. of Electr. & Comput. Eng., Portland State Univ., Portland, OR, USA ; Hawash, M. ; Perkowski, M.

This paper presents a new algorithm MP(multiple pass) to synthesize large reversible binary circuits without ancilla bits. The MMD algorithm requires to store a truth table (or a Reed-Muller -RM transform) as a 2^n vector for a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large scale reversible circuits (30-bits), which is not possible with existing algorithms. In addition, our unique multipass approach where the circuit is synthesized with various, yet specific, minterm orders yields optimal solution. The algorithm returns a description of the optimal circuit with respect to gate count or quantum cost. Although the synthesis process is relatively slower, the solution is found in real-time for smaller circuits of 8 bits or less

Published in:

Multiple-Valued Logic (ISMVL), 2010 40th IEEE International Symposium on

Date of Conference:

26-28 May 2010

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