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Layout Decomposition Approaches for Double Patterning Lithography

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4 Author(s)
Andrew B. Kahng ; Departments of Computer Science and Engineering, and Electrical and Computer Engineering, University of California at San Diego (UCSD), La Jolla, CA, USA ; Chul-Hong Park ; Xu Xu ; Hailong Yao

In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing. However, there exist pattern configurations for which pattern features separated by less than the minimum coloring spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using two layout decomposition approaches based on a conflict graph. First, node splitting is performed at all feasible dividing points. Then, one approach detects conflict cycles in the graph which are unresolvable for DPL coloring, and determines the coloring solution for the remaining nodes using integer linear programming (ILP). The other approach, based on a different ILP problem formulation, deletes some edges in the graph to make it two-colorable, then finds the coloring solution in the new graph. We evaluate our methods on both real and artificial 45 nm test-cases. Experimental results show that our proposed layout decomposition approaches effectively decompose given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:29 ,  Issue: 6 )