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Lower bounds on test resources for scheduled data flow graphs

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3 Author(s)
Parulkar, I. ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; Gupta, S.K. ; Breuer, M.A.

Lower bound estimations of resources at various stages of high-level synthesis are essential to guide synthesis algorithms towards optimal solutions. In this paper we present lower bounds on the number of test resources (i.e. test pattern generators, signature analyzers and CBILBO registers) required to test a synthesized data path using built-in self-test (BIST). The estimations are performed on scheduled data flow graphs and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of test resources to test itself

Published in:

Design Automation Conference Proceedings 1996, 33rd

Date of Conference:

3-7 Jun, 1996