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An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading

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3 Author(s)
Fard, S.F. ; Ukalta Eng., Edmonton, AB, Canada ; Alimohammad, A. ; Cockburn, B.F.

We present an ultracompact and fast hardware simulator for Rayleigh and Rician fading channels. To ensure numerical robustness and an efficient mapping onto hardware, the fading simulator uses the sum-of-sinusoids technique with N = 32 sinusoids added up to model each fading path. Fading samples are generated at a low rate and then are passed to an interpolator, which computes the final samples at the desired baseband rate. We propose a new time-multiplexed datapath that uses a differential approach. Instead of directly generating the fading samples, the datapath generates the discrete difference between fading samples. The proposed simulator is so compact that an entire 4 × 4 multiple-input-multiple-output (MIMO) fading channel can be implemented on a small fraction of a single field-programmable gate array (FPGA). On a Xilinx Virtex-4 XC4VLX200-11 FPGA, up to 1184 different paths can be simultaneously implemented while generating 1184 × 342 million 2 × 16-bit complex-valued fading samples per second.

Published in:

Vehicular Technology, IEEE Transactions on  (Volume:59 ,  Issue: 6 )

Date of Publication:

July 2010

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