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A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers

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2 Author(s)
Jian-Hao Lu ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Shen-Iuan Liu

A digital near-end crosstalk (NEXT) canceller merged with an analog equalizer for multi-lane serial-link receivers has been realized in 0.13 ¿m CMOS technology. By applying the proposed sign-sign block least-mean-square (SSB-LMS) circuit, a 5 Gb/s pseudorandom binary sequence (PRBS) of 2 31-1 suffered from both the channel loss and NEXT over 10- and 20-inch FR4 traces with the width of 5-mil and the spacing of 7-mil is successfully equalized. The measured bit error rate (BER) is 10-12 and the measured maximum peak-to-peak jitter is 49.7 ps. This chip occupies 0.56 × 0.76 mm2 and the whole circuit including buffers consumes 177 mW from a 1.2 V supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 2 )