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Product-representative “at speed” test structures for CMOS characterization

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2 Author(s)
M. B. Ketchen ; IBM Research Division, 2050 Rt. 52, Hopewell Junction, New York 12533, USA ; M. Bhushan

The design of product-representative test structures for measuring and characterizing CMOS circuit performance, power, and variability at speeds characteristic of present-day microprocessors is described. The current use of this set of test structures in the IBM partially depleted silicon-on-insulator CMOS technologies covers diagnostics in early process development, monitoring mature processes in manufacturing, enabling model-to-hardware correlation, and tracking product performance. The designs focus on measuring high-frequency performance early in the product fabrication cycle while minimizing test and data analysis time. The physical layouts are compact, facilitating placement in the chip. A subset of these test structures can be measured at the first metal level, while more complex designs use three or more metal layers. Most designs are compatible with standard in-line parametric test equipment, although a limited number of bench tests continue to play an important role. Differential measurement techniques are key to many of the test structure designs. Hardware data analysis also relies heavily on differencing schemes for relating MOSFET parameters and associated parasitic components to circuit delays in a self-consistent manner.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:50 ,  Issue: 4.5 )