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Design and verification of the IBM System z10 I/O subsystem chips

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11 Author(s)
Schlipf, T. ; IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany ; Helms, M.M. ; Ruf, J. ; Klein, M.
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In this paper, we discuss the microarchitecture, design, and verification of two IBM System z10™ I/O (input/output) chips: the z10™ hub chip, an InfiniBande host channel adapter with IBM-proprietary enhancements, and the InfiniBand memory bus adapter (MBA) chip, an InfiniBand-to-self-timed-interface fanout chip for attaching legacy I/O. Designing and verifying these chips presented many challenges. We describe our transaction- and packet-tracking concepts and the use of communication groups that emulate the behavior of logical partitions and their role in handling error and recovery cases. A novel technique has been employed to ensure that design implementation and architectural register definitions are consistent in a fully automated approach. Finally, we describe our approach to improving self-test coverage, which is based on an automated process of test-point insertion.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:53 ,  Issue: 1 )

Date of Publication:

Jan. 2009

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