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IBM System z10 performance improvements with software and hardware synergy

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7 Author(s)
Jackson, K.M. ; IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601, USA ; Wisniewski, M.A. ; Schmidt, D. ; Hild, U.
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This paper describes efforts to more fully exploit the synergy potential between hardware and software to improve performance on the IBM System z® platform. Although the IBM commitment to upward compatibility for System z mainframes prevents us from engaging in hardware generational tuning, software stack improvements aimed at one generation of hardware tend to increase in value for subsequent generations. This paper presents some of the software synergy efforts that were made to complement hardware design characteristics to improve performance and that will continue to be of benefit in future machine generations. Also presented is IBM z/OS® HiperDispatch management, which minimizes cache coherency penalties when dispatching work, and the new IBM System z10™ hardware instrumentation, the central processor measurement facility (CPMF), which supports software performance optimizations by providing counters and sampling and allowing the software to measure central processor activities to determine hotspots. The CPMF is nondisruptive, has low overhead, and can run in multiple logical partitions simultaneously.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:53 ,  Issue: 1 )