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We present the analysis of the interface-state generation and hole-trapping components of the VT shift in Si-oxynitride (SiON)-based p-MOSFETs due to the negative bias temperature instability. The amounts of interface-trap creation and hole trapping are separately assessed by three methods in this paper: 1) a separation method that isolates the contribution of interface traps, which assumes that hole trapping saturates very quickly during stress; 2) a novel transconductance (gm) technique which accurately characterizes the interface-trap generation; and 3) measurements of the VT after stress and comparison with a relaxation model using these methods. We find that interface-trap creation is accurately described by reaction-diffusion theory. Meanwhile, holes fill preexisting centers at a low oxide stress field, but trap generation occurs at a higher gate electric field. We suggest that the preexisting hole-trap centers are similar in pure SiO2 and SiON gate dielectrics and determine trapping characteristics at operation conditions.
Device and Materials Reliability, IEEE Transactions on (Volume:10 , Issue: 2 )
Date of Publication: June 2010