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A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS

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3 Author(s)
Pellerano, S. ; Radio Integration Res., Intel Corp., Hillsboro, OR, USA ; Madoglio, P. ; Palaskas, Y.

This paper presents a fractional frequency divider-by-1.25 and associated all-digital calibration circuitry. The divider can be used in a wireless transceiver to prevent direct or harmonic pulling of the VCO by the power amplifier. Timing errors between the quadrature phases used in the phase-rotating divider introduce fractional spurs at the output. In this design, the timing errors are measured with a stochastic time-to-digital converter with 20 fs resolution, and corrected to suppress output spurs. The fractional divider has been implemented in a 45 nm CMOS LP process and its core dissipates an estimated 17 mA current from a 1.1 V supply. After calibration, fractional spurs are on average below -59 dBc and -50 dBc (¿ ~ 2 dB over 10 samples) with a 2.5 and 3.8 GHz output frequency respectively. Calibration performance has been confirmed for temperatures from -20°C up to 85°C. The low spur level facilitates radio co-existence with no need for additional filtering. This makes this divider a good candidate for WiFi and WiMAX radios up to 3.8 GHz.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 12 )

Date of Publication:

Dec. 2009

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