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An advance in folding-interpolating analog-to-digital converters (ADCs) is demonstrated which simplifies their extension to higher resolution by building the converter out of identical but scaled pipelined cascaded folding stages. In this unified folding architecture the parallel coarse channel has been eliminated by recursively using the previous folding stage as the coarse channel for each following cascaded stage. This new architecture is demonstrated in a 10-bit ADC using six cascaded folding-by-3 stages with a total folding order of 729. At 1.0 GS/s, this interleave-by-2 ADC achieves <Â±0.2 LSB DNL, Â¿ Â±0.5 LSB INL, 9.2 ENOB at 100 MHz input, 9.1 ENOB at Nyquist, and 8.8 ENOB at 1 GHz input. The value at FIN = 1 GHz is 1 ENOB higher than any value published to date. The power consumption from a single 1.8 V supply is 1.2 W/channel which includes the LVDS drivers for this dual-channel (I and Q each running at 1 GS/s) ADC.
Date of Publication: Dec. 2009