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Through silicon via (TSV) is considered today as the third dimension interconnect opening new perspectives in term of 3D integration. Design, material and process recommendations are required to achieve 3D stacked dies and evaluate electrical performance of such chips. As a consequence, equivalent models of this incontrovertible key component become more and more mandatory. In this paper, a full parametric and frequency dependent model of high aspect ratio TSV is proposed based on both electromagnetic (EM) simulations and RF measurements. This model enables to extract TSV resistance, self inductance, oxide capacitance and parasitic elements due to the finite substrate resistivity. Its full compatibility with SPICE solvers allows the investigation of TSV impact on circuit performance.