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Reduced scan shift: a new testing method for sequential circuits

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3 Author(s)
Y. Higami ; Fac. of Eng., Osaka Univ., Japan ; S. Kajihara ; K. Kinoshita

This paper presents a new testing method for sequential circuits, called reduced scan shift, which generates short test sequences. In this method, only part of flip-flops close to the scan input line are controlled and another part of flip-flops close to the scan output line are observed by scan shift operations as small as possible. For the purpose of reducing scan shift operations, the following points are considered: (1) how to decide target faults which each test vector should detects, (2) how to arrange flip-flops in the scan chain, (3) how to decide the order of test vectors. Experimental results for ISCAS'89 benchmark circuits are given to show the effectiveness of this method

Published in:

Test Conference, 1994. Proceedings., International

Date of Conference:

2-6 Oct1994