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Layout synthesis for datapath designs

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2 Author(s)
Buddi, N. ; Dept. of Electr. Eng., Portland State Univ., OR ; Chrzanowska-Jeske, M.

DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-slice, such that the regularity of datapath circuits is presented and the number of channels occupied by a control signal is minimized. In addition, we propose a novel window-based heuristic for global routing of multipin nets. VHDL interface makes DPLAYOUT a general tool which can be easily integrated with any high-level synthesis system. This paper describes the heuristics developed for placement and global routing of a single bit-slice. We compared the area and run-time efficiency of the proposed heuristics with conventional methods and the results show a significant improvement

Published in:

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Date of Conference:

18-22 Sep 1995