Skip to Main Content
ESD failure mechanisms, specific for charged device model (CDM) stress, are discussed for an input protection structure in a smart power technology showing unexpected dependency of CDM robustness on design variations. This paper demonstrates that factors like package parameters, substrate resistance and parasitic pn-junctions and physical layers have a significant influence on circuits' CDM behavior. The importance of consideration and accurate modeling of these factors for achieving meaningful conclusions for failure mechanisms and CDM robustness from circuit simulation is illustrated. For validation of the proposed simulation setup, results from circuit simulation are compared to measurements and device simulation.