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ESD design automation for a 90nm ASIC design system

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7 Author(s)
Ciaran J. Brennan ; IBM Microelectronics, 1000 River Road, MS863M, Essex Junction, VT 05452 USA ; Joseph Kozhaya ; Robert Proctor ; Jeffrey Sloan
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Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.

Date of Conference:

19-23 Sept. 2004