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High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability

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2 Author(s)
Sying-Jyan Wang ; Dept. of Comput. Sci. & Eng., Nat. Chung Hsing Univ., Taichung, Taiwan ; Tung-Hua Yeh

A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with hierarchical test-pattern generation for embedded modules, guarantees a 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay-fault coverage is usually attributed to the fact that a two-pattern test for delay testing cannot be delivered to modules under test in two consecutive cycles. To solve the problem, we propose an HLTS method that ensures that valid test pairs can be sent to each module through synthesized circuit hierarchy. Experimental results show that this method achieves 100% fault coverage for transition faults in modules; in contrast, the fault coverage in circuits synthesized by a left-edge-algorithm-based allocation algorithm is rather poor. The area overhead due to this method ranges from 1% to 10% for 16-b datapath circuits. On the other hand, hierarchical test patterns cannot provide good delay-fault coverage for faults in interconnection structure and registers. The reason is that some control sequences required for delay-fault detection cannot be provided by the controller. We propose two design-for-testability insertion methods to deal with this problem. Experimental results show that, on the average, at least 11% higher delay-fault coverage is achieved by these methods.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:28 ,  Issue: 10 )