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Winning with Pinning in NoC

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3 Author(s)
Ahmed Abousamra ; Comput. Sci. Dept., Univ. of Pittsburgh, Pittsburgh, PA, USA ; Rami Melhem ; Alex Jones

In chip multiprocessors (CMPs), on-chip interconnect carries data and coherence traffic exchanged between on chip cache banks. Reducing communication latency is critical for improving the performance of applications running on CMPs. Communication latency is affected by network design, cache organization, and application design. Previously proposed techniques for reducing router latency using express virtual channels or hybrid circuit switching effectively reduce communication latency. However, our analysis of communication traffic of a suite of scientific and commercial workloads on a 16-core cache coherent CMP showed low utilization of circuits due to repeated establishment and tear down of circuits. In this paper, we explore circuit pinning, an efficient way of establishing circuits that promotes higher circuit utilization, adapts to changes in communication characteristics, simplifies network control, and allows smarter routing techniques due to the stability of configured circuits. Comparison with state of the art packet switched and hybrid circuit switched interconnects across different cache organizations demonstrates the benefits of our technique.

Published in:

2009 17th IEEE Symposium on High Performance Interconnects

Date of Conference:

25-27 Aug. 2009