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Cache performance of vector processors

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2 Author(s)
K. So ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; V. Zecca

An instruction-level simulator for IBM 3090 with VF (vector facility) has been developed for studying the performance of vector processors and their memory hierarchies. Results of a study of the locality of several large scientific applications are presented. The cache miss ratios of vectorized applications are found to be almost equal to those of their original scalar executions. Moreover, both the spatial and temporal locality of these applications (in scalar and vector executions) are strong enough to show a sufficiently high hit ratio on conventional cache structures

Published in:

Computer Architecture, 1988. Conference Proceedings. 15th Annual International Symposium on

Date of Conference:

30 May-2 Jun 1988