The assembly-language translation of the operational flight program for a tactical fighter plane's radar data processor

As military budgets shrink, military contractors are under increasing pressure to produce high performance systems for the lowest possible cost. For new weapons systems, this pressure generally has meant exploiting the economies of scale of standardized, military-approved microprocessor chips. As currently-deployed systems age, an equal need exists to tap these same economies of scale to extend the useful lives of older defense systems in a cost-effective manner. Upgrading a processor-based component of a defense system involves both hardware and software migration tasks. The software migration task typically requires the translation of assembly-language programs from older complex instruction set computers (CISC) to the native code of the reduced instruction set computers (RISC) used in designs today. Although the migration of hardware is not without its difficulties, it is aided by the fact that CPU speeds and complexities provide tremendous flexibility to hardware designers of today compared with their counterparts of 20 to 30 years ago. However, the translation of assembly-language programs written for proprietary systems of 20+ years ago still presents tremendous difficulties and is often the primary reason why such hardware/software upgrades are not attempted. This paper discusses the software upgrade methodology used to translate the operational flight program (OFF) of the fielded radar data processor (RDP) unit of an advanced radar system aboard a tactical fighter plane. In particular, the paper concentrates on the translation and debugging processes used to re-host the OFF of the RDP onto a new hardware platform designed around the Intel i960 RISC microprocessor architecture.