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A simulation study of two-level caches

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2 Author(s)
R. T. Short ; DECwest Eng., Bellevue, WA, USA ; H. M. Levy

A trace-driven simulation study to examine the effect of a two-level cache hierarchy in uniprocessors is reported. A simulation model of a multiple-cycle-per-instruction processor was constructed to estimate the total cycles required to execute a synthetic benchmark. Results show that a second-level cache can be used to increase system performance when main memory access times are large relative to CPU cycle time. For example, the addition of a four-cycle 64 K second-level cache following a one-cycle, 8 K first-level cache increases performance by 15% when used in a system with a 15-cycle primary memory. Second-level caches are shown to be particularly effective when used behind small on-chip caches; adding an 8 K second-level to a 1 K first-level increases performance by 26%, assuming similar parameters. The performance impact of different write strategies and separate instruction and data caches are also evaluated

Published in:

Computer Architecture, 1988. Conference Proceedings. 15th Annual International Symposium on

Date of Conference:

30 May-2 Jun 1988