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A double-level-V/sub th/ select gate array architecture for multi-level NAND flash memories

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3 Author(s)
Takeuchi, K. ; ULSI Res. Labs., Toshiba Corp., Kawasaki, Japan ; Tanaka, T. ; Nakamura, H.

This paper first explains that gate array noise during a bit-by-bit program verify operation, named source line noise, is estimated to have a crucial adverse effect on the threshold voltage (V/sub th/) control and causes a serious problem in Multi-Level NAND Flash Memories. Then a new array architecture, a Double-Level-V/sub th/ Select Gate Array Architecture, is introduced to eliminate this noise without cell area penalty.

Published in:

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Date of Conference:

8-10 June 1995

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