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A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-memory

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3 Author(s)
T. Yamauchi ; ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan ; Y. Morooka ; H. Ozaki

We propose a high speed and low power data transfer scheme for the wide internal data bus of an AS-Memory using the asynchronous compressed pulse width modulation (AC-PWM) technique and an automatic gain controlled (AGC) amplifier. The maximum bit rate per bus of AC-PWM increases by 12 times that of the conventional 100MHz data bus. The AGC amplifier achieves a fast data output while reducing by 1/3 the standby current. The proposed architecture is a key advance in the future development of AS-Memories.

Published in:

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Date of Conference:

8-10 June 1995