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A novel SRAM cell architecture for sub-1-V high-speed operation is proposed without using either low-V/sub th/ MOSFETs or modifying the cell layout pattern. A source-line connected to the source terminals of driver MOSFETs is controlled to be negative and floating in the read- and write-cycles, respectively. The cell-access time is reduced to 1/4-1/2 at a supply voltage of 0.5-1.0 V. Limiting the bit-line swing reduced the writing power needed to charge the bit-lines to 1/10, and it realizes a faster write-recovery. The feasibility of low-power 100 MHz operation over a wide range of supply voltages is demonstrated.