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A 2-ns, 5-mW, synchronous-powered static-circuit fully associative TLB

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4 Author(s)
H. Higuchi ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; S. Tachibana ; M. Minami ; T. Nagano

Virtual memory is used in most high-performance computer systems to extend the address space. Virtual addresses are translated by the system into physical addresses at run-time. The translation is usually accelerated by special hardware called a translation look-aside buffer (TLB). Thus, TLBs are required for high-speed operation. In conventional high-speed TLBs, set-associative memories are utilized. But they need a large chip area. Fully associative TLBs which use content addressable memories (CAM) realize smaller chip areas. But slow circuit speed and large power dissipation are drawbacks in large entry-TLBs. This paper describes high-speed, low-power fully associative TLBs which do not need any signal lines added to conventional TLBs by using a newly developed matched signal and reference signal generator circuits.

Published in:

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Date of Conference:

8-10 June 1995