A 286 MHz 64-bit floating point multiplier with enhanced CG operation

High speed floating point (FP) multipliers are essential for high speed calculation systems because increasingly large numbers of FP multiplications must be carried out in various applications such as scientific calculation and computer graphics (CG). CG, in particular, requires enormous amount of FP multiplications to obtain high quality images required for multimedia systems. To realize high speed, the critical path delay must be minimized. In this paper, we discuss a method to shorten the delay time of the critical path. Then we present an FP multiplier design based on the method. A special function for CG is also implemented without increasing the critical path delay. Finally, we show the fabrication and test results of the FP multiplier.