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A 375 MHz 1 /spl mu/m CMOS 8-bit multiplier

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2 Author(s)
Rogenmoser, R. ; Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland ; Qiuting Huang

A signed 8-bit pipelined multiplier has been implemented in a standard 1.0 /spl mu/m CMOS process. It was successfully tested up to 375 MHz. This performance was achieved using the true single-phase clocking technique, fine-grain pipelining, and merging the combinational logic into the pipeline registers.

Published in:

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Date of Conference:

8-10 June 1995