Cart (Loading....) | Create Account
Close category search window
 

A 0.4 /spl mu/m 1.4 ns 32b dynamic adder using non-precharge multiplexers and reduced precharge voltage technique

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Inoue, A. ; Fujitsu Labs. Ltd., Kanagawa, Japan ; Kawabe, Y. ; Asada, Y. ; Ando, S.

This paper describes fast 32-bit dynamic adder using nonprecharge multiplexers and reduced precharge voltage technique. Design adopting novel multiplexers reduces transistor count, resulting in the reduction of total parasitic capacitance. Reduced precharge voltage makes the discharge time shorter. Experimental circuit has been fabricated using 0.4 /spl mu/m CMOS technology and we confirmed the delay of 1.4 ns at the supply voltage of 3.3 V at room temperature.

Published in:

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Date of Conference:

8-10 June 1995

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.