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A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification

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2 Author(s)
Weirong Jiang ; Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Viktor K. Prasanna

Multi-field packet classification is a critical function that enables network routers to support a variety of applications such as firewall processing, quality of service differentiation, traffic billing, and other value added services. Explosive growth of Internet traffic requires the future packet classifiers be implemented in hardware. However, most of the existing packet classification algorithms need large amount of memory, which inhibits efficient hardware implementations. This paper exploits the modern FPGA technology and presents a partitioning-based parallel architecture for scalable and high-speed packet classification. We propose a coarse-grained independent sets algorithm and then combine it seamlessly with the cross-producting scheme. After partitioning the original rule set into several coarse-grained independent sets and applying the cross-producting scheme for the remaining rules, the memory requirement is dramatically reduced. Our FPGA implementation results show that our architecture can store 10 K real-life rules in a single state-of-the-art FPGA while consuming a small amount of on-chip resources. Post place and route results show that the design sustains 90 Gbps throughput for minimum size (40 bytes) packets, which is more than twice the current backbone network link rate.

Published in:

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors

Date of Conference:

7-9 July 2009