By Topic

Performance Analysis of Guaranteed Throughput and Best Effort Traffic in Network-on-Chip under Different Traffic Scenario

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Paliwal, K.K. ; Dept. of Comput. Eng., Malaviya Nat. Inst. of Technol., Jaipur, India ; Gaur, M.S. ; Laxmi, V. ; Janyani, V.

Network on Chip (NoC) paradigm has made it possible to concurrently run multiple applications on IP-core based System on Chip. It is therefore necessary to predict the multi-processor systems-on-chip communication, which is a critical issue and needs to be addressed by the right mix of soft and hard real-time guarantees. To meet this requirement state of the art packet switched networks-on-chip (NoC) provide different levels of quality of service (QoS) such as best effort (BE) and guaranteed throughput (GT). This paper presents a novel scheme which compares and evaluates the performance of guaranteed throughput and best effort traffic in Network-on-Chip under different synthetic traffic generators and highlights its dependence in terms of latency on the type of traffic patterns and on the topology selection (mesh and torus) of Network on Chip. It also explores the effect of various routing function such as dimension order, planar adapter, romm and valiant on latency of GT and BE traffic for mesh topology.

Published in:

Future Networks, 2009 International Conference on

Date of Conference:

7-9 March 2009