CMOS VCOs for PLL frequency synthesis in GHz digital mobile radio communications

We report on a CMOS inductorless VCO design with an emphasis on low-noise, low-power, gigahertz-range circuits suitable for portable wireless equipment. The paper considers three structures-one simple ring oscillator and two differential circuits. The design methodology followed optimization for high-speed and low-power consumption. The measurement results of three VCOs implemented in 1.2 /spl mu/m CMOS technology verify the simulation predictions. The simplest VCO architecture exhibits 926 MHz operation with -83 dBc/Hz phase noise (100 kHz carrier offset) and 5 mW (5 volts) power consumption.