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Current integrating receivers for high speed system interconnects

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2 Author(s)
S. Sidiropoulos ; Center for Integrated Syst., Stanford Univ., CA, USA ; M. Horowitz

This paper presents a high speed receiver design that utilizes current integration in order to increase its noise immunity. The integration of current on a capacitor based on the incoming signal voltage effectively averages the incoming signal over its valid time period, therefore filtering out high frequency noise. An experimental design illustrating the concept has been fabricated in a 1.2 μm CMOS technology. The receiver dissipates 2.7 mW of power operating from a 5-V supply, achieves error free operation at a clock frequency of 250 MHz, and occupies 60×450 μm2 of silicon area

Published in:

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Date of Conference:

1-4 May 1995