Referenced Items are not available for this document.
A pipelined 32-bits integer arithmetic unit with dynamic accuracy is described, that supports addition/subtraction, multiplication/division, power/root and a number of mixed operations such as sum of squares directly in hardware, and is easily extended for floating-point and adaptive accuracy computations. In a 0.8 μm CMOS technology, this module houses 3k transistors on a 2.5 mm2 area and operates at about 100 MHz external clock
Published in:
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Date of Conference: 1-4 May 1995
- Page(s):
- 33 - 36
- Meeting Date :
- 01 May 1995-04 May 1995
- Print ISBN:
- 0-7803-2584-2
- INSPEC Accession Number:
- 5161673
- Conference Location :
- Santa Clara, CA
- Digital Object Identifier :
- 10.1109/CICC.1995.518132
- Product Type:
- Conference Publications
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