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A 0.9 V to 5 V mixed-voltage I/O buffer using NMOS clamping technique

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3 Author(s)
Chua-Chin Wang ; Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan ; Jen-Wei Liu ; Ron-Chi Kuo

A 0.9 V to 5 V (0.9/1.2/1.8/2.5/3.5/5 V) mixed-voltage I/O buffer with NMOS clamping technique is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 3 times VDD voltage level signal without gate-oxide overstress hazard. Besides, the leakage current effect is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to 140/120/120/120/80/40 Mbps for 5/3.3/2.5/1.8/1.2/0.9 V, respectively, with a given capacitive load of 10 pF.

Published in:
IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on

Date of Conference: 18-20 May 2009

Page(s):
29 - 32
E-ISBN :
978-1-4244-2934-9
Print ISBN:
978-1-4244-2933-2
INSPEC Accession Number:
10779765
Conference Location :
Austin, TX
Digital Object Identifier :
10.1109/ICICDT.2009.5166258
Product Type:
Conference Publications

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