Custom design in a low-power/high-performance ASIC world

Aggressive design cycle requirements are making it increasingly difficult to deploy custom and even semi-custom design techniques in consumer ASIC's. However, market requirements continue to push IP implementation teams harder and harder for increased performance and reduced power consumption. Given these two conflicting trends, new design methodologies are required, such that IP design teams can meet market expectations, without the large staffs and long schedules that have traditionally characterized custom design. This presentation reviews several high-ROI methodologies which can be utilized in this design environment to improve implementations without dramatic impact to budgets and schedules.