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A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs

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2 Author(s)
Kinam Kim ; Semicond. R&D Center, Samsung Electron. Co., Ltd., Hwaseong, South Korea ; Jooyoung Lee

Data retention time for ultimate DRAMs with an extremely scaled-down cell size has been investigated. The entire memory cells can be discretely categorized by two groups: leaky cells or normal cells, and the main distribution representing the normal cells shows longer than 40 s of the mean retention time. The leaky cells are mainly originated by trap-assisted gate-induced drain leakage currents depending on trap energy dispersion. Through analyses of full chip retention failure curves and interface trap density ( Dit*) measurements, we propose that the tail distribution will be diminished and separated from the main distribution as the cell size shrinks into a true nanoscale. As a result, the retention time is eventually to be determined by the main distribution function only.

Published in:

IEEE Electron Device Letters  (Volume:30 ,  Issue: 8 )