By Topic

First Wafer Delay and setup: How to measure, define and improve First Wafer Delays and setup times in semiconductor fabs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Radloff, S. ; Intel Corp., Andover, MA, USA ; Abravanel, M. ; Rhoads, B. ; Steeg, D.
more authors

First wafer delay (FWD) has been identified as a barrier to reduced fab cycle time and increased equipment productivity. As such, initiatives to reduce first wafer delay have been proposed as a focal point for next generation semiconductor fabs, including both 450 mm fabs as well as ldquo300 mm Primerdquo factories. FWD and setup time are major detractors for cycle time reduction, in particular for small lot manufacturing. The definition of FWD, causes, as well as methods for improving FWD are discussed, in addition to recommendations for future equipment and factory design.

Published in:

Advanced Semiconductor Manufacturing Conference, 2009. ASMC '09. IEEE/SEMI

Date of Conference:

10-12 May 2009