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Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs

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1 Author(s)
Andy Gean Ye ; Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada

Mapping digital circuits onto field-programmable gate arrays (FPGAs) usually consists of two steps. First, circuits are mapped into look-up tables (LUTs). Then, LUTs are mapped onto physical resources. The configuration of LUTs is usually determined during the first step and remains unchanged throughout the second. In this paper, we demonstrate that by reconfiguring LUTs during the second step, one can increase the flexibility of FPGA routing resources. This increase in flexibility can then be used to reduce the implementation area of FPGAs. In particular, it is shown that, for a logic cluster with I inputs and N k-input LUTs, a set of N??k (I+N-k+1):1 multiplexers can be used to connect logic cluster inputs to LUT inputs while maintaining logic equivalency among the logic cluster I/Os. The multiplexers (called a local routing network) are shown to be the minimum required to maintain logic equivalency. Comparing to the previous design, which employs a fully connected local routing network, the proposed design can reduce logic cluster area by 3%-25% and can reduce a significant amount of fanouts for logic cluster inputs.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:18 ,  Issue: 1 )