Referenced Items are not available for this document.
The implementation of digital signal processor circuits via self-timed techniques is currently a valid alternative to solve some problems encountered in synchronous VLSI circuits. However, a main difference between synchronous and asynchronous circuits is the hardware resources needed to implement asynchronous circuits. This communication presents four less-costly alternatives to a previously reported linear self-timed architecture, and their application in the design of FIFO memories. Furthermore, the integration and characterization in the laboratory of prototypes of these FIFOs are presented
Published in:
Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on
Date of Conference: 30-31 May 1995
- Page(s):
- 14 - 23
- Meeting Date :
- 30 May 1995-31 May 1995
- Print ISBN:
- 0-8186-7098-3
- INSPEC Accession Number:
- 5044968
- Conference Location :
- London
- Digital Object Identifier :
- 10.1109/WCADM.1995.514638
- Product Type:
- Conference Publications
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