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New CMOS VLSI linear self-timed architectures

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6 Author(s)
Acosta, A.J. ; Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain ; Bellido, M. ; Valencia, M. ; Barriga, A.
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The implementation of digital signal processor circuits via self-timed techniques is currently a valid alternative to solve some problems encountered in synchronous VLSI circuits. However, a main difference between synchronous and asynchronous circuits is the hardware resources needed to implement asynchronous circuits. This communication presents four less-costly alternatives to a previously reported linear self-timed architecture, and their application in the design of FIFO memories. Furthermore, the integration and characterization in the laboratory of prototypes of these FIFOs are presented

Published in:

Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on

Date of Conference:

30-31 May 1995

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