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Dynamic data retention and implied design criteria for floating-body SOI DRAM

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3 Author(s)
Dongwook Suh ; Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA ; Fossum, J.G. ; Pelella, M.M.

A physical MOSFET model in SOISPICE is used to characterize dynamic data retention in PD/SOI DRAM cells. Simulations show that transient parasitic BJT current underlies peculiar data retention, and they suggest how periodic body discharge effected by data refresh with a high flatband-voltage cell transistor can render PD/SOI technology viable and attractive for gigabit DRAM applications.

Published in:

Electron Device Letters, IEEE  (Volume:17 ,  Issue: 8 )