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A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator

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2 Author(s)
Ahmed Gharbiya ; Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON ; David A. Johns

We demonstrate a 12-bit 0-3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 mum CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 & dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0-3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).

Published in:

IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 7 )