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A 35 Gbit/s throughput 64 kbit CMOS buffer SRAM

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2 Author(s)
Alowersson, J. ; Dept. of Comput. Eng., Lund Univ., Sweden ; Andersson, P.

A 64 kbit 0.8-μm pure CMOS buffer memory with 256 bit word-length and 3.6 ns cycle time, allowing 35 Gbit/s throughput, is presented. The memory consumes 1.5 W at the maximum frequency. The short cycle time is achieved through the use of a synchronously pipelined address decoder with one internal level of latches. The address decoder, based on TSPC latches, is described in detail

Published in:

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Date of Conference:

5-8 May 1996