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Power management technique for 1-V LSIs using embedded processor

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3 Author(s)
Shigematsu, S. ; NTT LSI Labs., Atsugi, Japan ; Mutoh, S. ; Matsuya, Y.

A new power management technique is proposed for low-power, high-speed LSIs. This technique reduces the power consumption and enhances the performance of an LSI by using an embedded small processor to control the sleep modes and the processing of the LSI. Using this technique for a low-power DSP, the total power is reduced to about 10% of one without this technique, while maintaining the speed performance in 1-V LSIs

Published in:

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Date of Conference:

5-8 May 1996