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A new approach to pipeline FFT processor

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2 Author(s)
Shousheng He ; Dept. of Appl. Electron., Lund Univ., Sweden ; Torkelson, M.

A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-22 algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log4N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL

Published in:

Parallel Processing Symposium, 1996., Proceedings of IPPS '96, The 10th International

Date of Conference:

15-19 Apr 1996

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