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Noise suppression scheme for giga-scale DRAM with hundreds of I/Os

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5 Author(s)
Takashima, D. ; ULSI Res. Center, Toshiba Corp., Kawasaki, Japan ; Oowaki, Y. ; Watanabe, S. ; Ohuchi, K.
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A new Constant Current Voltage-Down Converter and a new Partially Inverted data BUS Architecture are proposed. The proposed VDC reduces Vdd1/Vss1 noise to less than 20%, and the proposed BUS architecture reduces Vdd1/Vss1 noise to about 1/n using only n-1 bit flag signals.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996