Demonstration of 5T SRAM and 6T dual-port RAM cell arrays

This paper describes new circuit techniques that provide robust operations for a five transistor, single bitline SRAM cell design. The techniques have been implemented in an array of six transistor memory cells and operated as a dual-port RAM. The array has been fabricated using 0.6 /spl mu/m CMOS technology, and the test results show the array is capable of operating as a dual-port memory over a wide voltage supply range.